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Writer's pictureMackenzie Hawkins

Equivalent Time Sampling Oscilloscope

To further expand my skill-set and gain insight into high-speed signal designs, I wanted to replicate a design by Ted Yapo for a equivalent time sampling oscilloscope. Rather that simply copying the design, I modified the layout such that the oscilloscope could function as a shield on an Arduino Mega. This design choice served two purposes, first reducing the design complexity and cost because the microcontroller is offloaded to an existing board, and secondly to speed up the development time by allowing for the use of the simple Arduino environment.

The goal of this project was to learn about design aspects such as high-speed trace routing (with theoretical operation up to 8GHz this was very critical), clock edge alignment, discrete implementation of a successive-approximation-register (SAR) analog-to-digital converter, and low-voltage differential signaling.

The design was done using Altium Designer as seen below. The controlled impedance traces on the top layer were intended to be microstrip transmission lines but in an effort to reduce noise and cross-talk, via-stitching to ground around the traces to ground was done. This changes the transmission line from a microstrip to a coplanar waveguide thus changing the characteristic impedance of the trance. Where of not this is a negligible change requires further investigation but it part of the learning process this project was intended for.

The PCB was manufactured through JLC using their controlled impedance 2313 stack up.

When I was interviewing for a new position in the end of 2019 I was asked to compose a technical presentation on a topic of my choosing. At the time, this is the project I was focusing my efforts and decided to make the presentation on this design.

 

Future of the project:

After a second revision of the board was ordered do to an incorrectly sized footprint

the board is functioning as intended. The code needs to be further developed to execute the SAR algorithm and a fast edge source needs designed or procured to fully test functionality.

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